1. Field of the Invention
The present invention relates to a memory cell and a manufacturing method thereof, and more particularly, to a memory cell with an L-shaped patterned material layer and a manufacturing method thereof.
2. Description of the Prior Art
Semiconductor memory devices used for storing data can be divided into volatile devices and non-volatile devices. Volatile memory devices lose data stored therein when a supply voltage is interrupted, while non-volatile memory devices retain the data stored therein even if the supply voltage is interrupted. Accordingly, non-volatile memory devices are widely used when the supply voltage is not always applied or often interrupted, or when a device requires only a low voltage, such as a mobile telephone, a memory card for storing music and/or image data, and other application devices.
Cell transistors of the non-volatile memory device have a stacked gate structure. The stacked gate structure includes a gate insulating layer which is sequentially stacked on a channel region of the cell transistor, a floating gate electrode, an insulating layer between gates, and a control gate electrode. The non-volatile memory device often can be formed by a silicon layer in which a channel region is formed, an oxide layer which forms a tunneling layer, a nitride layer which is used as a charge trapping layer, an oxide layer which is used as a blocking layer, and a silicon layer which is used as a control gate electrode. This structure is referred to as a silicon-oxide-nitride-oxide-silicon (or SONOS) cell structure.
A conventional SONOS memory cell can perform forward read and reverse read to store electrons in the right side or left side of the charge trapping layer. With the shrinkage of semiconductor devices, however, the size of the charge trapping layer is reduced and the electrons stored therein are becoming fewer as well. This results in increased errors of the memory devices when programming or reading devices and thus affects the reliability of semiconductor products.